1. Field of the Invention
The present invention relates to a triplet decoding process and more particularly, to a triplet decoding circuit and a triplet decoding method that decode or expand the data of a "triplet", which is generated by compressing three original data into a single one for the purpose of data amount decrease, to restore the original data.
2. Description of the Prior Art
Image data for television fields and audio data for Compact Disk (CD) fields are vast in amount. Therefore, to perform efficient transmission of these data or efficient recording of these data on various media such as magnetic tapes, magnetic disks, and optical disks, they are usually compressed prior to transmission or recording. Then, the compressed data are expanded or decoded in the receiving side or in reading the data to restore or return the three original data.
With this type of data compression/expansion technology, three original data in a certain range are converted or coded into a signal one to produce a compressed data known as a "triplet", and the data of the triplet is than expanded or decoded to restore the original three data as necessary. This data compression/expansion technology has an advantage that the data length of the triplet data is shorter than the total length of the three original data.
As the triplet data, a triplet of a decimal number "3", which is the sum of three original data each multiplied by a different value of power of 3, and a triplet of a decimal number "5", which is the sum of three original data each multiplied by a different value of power of 5, have been often used.
If a triplet of 3 is represented by "Y3", the triplet data Y3 is defined as the sum of three original data M1, M2, and M3 multiplied respectively by decimal number "9" (=3.sup.2), "3" (=3.sup.1), and "1" (=3.sup.0), as shown in the following equation (1). EQU Y3=9.times.M1+3.times.M2+M3 (1)
In the equation (1), each of the original data M1, M2, and M3 has a value of 0, 1, or 2 in the decimal number system. Thus, the triplet data Y3 may have any value ranging from 0 to 26 (i.e., 0.ltoreq.Y3.ltoreq.26).
The maximum value of Y3, i.e., a decimal number "26", is represented as "11010" in the binary number system, which requires five bits. On the other hand, each of the three original data M1, M2, and M3 is any one of the decimal numbers 0 (=00), 1 (=01), and 2 (=10), each of which necessitates two bits. Therefore, six bits are necessary in total to represent the three original data M1, M2, and M3. Accordingly, the triplet data Y3 is smaller in data amount than the sum of the three original data M1, M2, and M3 by one bit.
Likewise, if a triplet of 5 is represented by "Y5", the triplet data Y5 is defined as the sum of three original data M1, M2, and M3 respectively multiplied by decimal number "25" (=5.sup.2), "5" (=5.sup.1), and "1" (=5.sup.0), as shown in the following equation (2). EQU Y5=25.times.M1 +5.times.M2+M3 (2)
In the equation (2), each of the original data M1, M2, and M3 has a value of 0, 1, 2, 3, or 4 in the decimal number system. Thus, the triplet data Y5 may have any value ranging from 0 to 124 (i.e., 0.ltoreq.Y5.ltoreq.124).
The maximum value of Y5, i.e., a decimal number "124", is represented as "1111100" in the binary number system, which requires seven bits. On the other hand, each of the three original data M1, M2, and M3 is any one of the decimal numbers 0 (=000), 1 (=001), 2 (=010), 3 (=011), and 4 (=100), each of which necessitates three bits. Therefore, nine bits are necessary in total to represent the three original data M1, M2, and M3. Accordingly, the triplet data Y5 is smaller in data amount than the sum of the three original data M1, M2, and M3 by two bits.
Next, the above conventional triplet technology will be described in greater detail below with the use of FIG. 1, FIGS. 2A to 2I, and FIGS. 3A to 3I.
As shown in FIG. 1, a conventional triplet decoding circuit has a serial input terminal 100 that receives serially a triplet data Y (e.g., Y3 or Y5) in the binary number system and a selection-signal input terminal 103 that receives a selection signal S. The triplet data Y and the selection signal S are inputted in synchronization with a specific clock signal. The binary triplet data Y is serially inputted into the terminal 100 from its most significant bit (MSB) to its least significant bit (LSB).
According to the selection signal S, a first constant generator 102 generates a negative constant C1 of "-3" (decimal) for the triplet Y3 and of "-5" (decimal) for the triplet Y5 to output to a first adding circuit 105. Similarly, a second constant generator 107 generates a negative constant C2 of "-3" for the triplet Y3 and of "-5" for the triplet Y5 to a second adding circuit 110. Thus, each of the first and second adding circuits 105 and 110 practically performs a subtraction operation of "3" or "5".
The triplet data Y as the input data through the serial input terminal 100 is inputted into a first shift register 101 in sequence in synchronization with the clock signal, outputting a first register output R1 in parallel. This output R1 contains the content of the register 101 at that time. This output R1 is sent to a first selector 114 and at the same time, sent to the first adding circuit 105 to be added to the first constant C1 from the first constant generator 102.
The first adding circuit 105 practically subtracts the first constant C1 from the first register output R1, outputting a first subtraction result A1 to the first data selector 114. The first subtraction result A1 may be fed back to the first shift register 101 at a specific timing.
The first adding circuit 105 further outputs a first borrow output B1 generated by the subtraction operation of the first register output R1 and the first constant C1. The first borrow output B1 is sent to a second shift register 106 and then, inputted into the register 106 after inverting its polarity through a serial input terminal of the register 106. The first borrow output B1 may be fed back to the first shift register 101 at a specific timing.
The first borrow output B1 as the input data through the serial input terminal 109 is inputted into the second shift register 106 in sequence in synchronization with the clock signal, generating a second register output R2 in parallel. This output R2 is sent to a second selector 115 and at the same time, sent to a second adding circuit 110 to be added to the second constant C2 from the second constant generator 107.
The second adding circuit 110 practically subtracts the second constant C2 from the second register output R2, outputting a second subtraction result A2 to the second selector 114. The second subtraction result A2 may be fed back to the second shift register 106 at a specific timing.
The second adding circuit 110 further outputs a second borrow output B2 generated in the subtraction operation of the second register output R2 and the second constant C2. The second borrow output B2 is sent to a third shift register 111 and then, inputted into the register 111 after inverting its polarity through a serial input terminal 112 of the register 111. The second borrow output B2 may be fed back to the second shift register 106 at a specific timing.
The first selector 114 selects one of the first register output R1 and the first subtractions result A1 to output to a first output terminal 104 as a first selector output L1 according to the value of the first borrow output B1. The lower two bits of the first selector output L1 represent the original decimal number M3 contained in the triplet data Y.
The second selector 115 selects one of the second register output R2 and the second subtraction result A2 to output to a second output terminal 108 as a second selector output L2 according to the value of the second borrow data B2. The lower two bits of the second selector output L2 represent the original decimal numbers M2 contained in the triplet Y.
The third shift register 111 outputs a third register output R3 to a third output terminal 113. The lower two bits of the third register output R3 represent the original decimal numbers M1 contained in the triplet data Y.
Subsequently, the operation of the conventional triplet decoding circuit shown in FIG. 1 is explained below referring to FIGS. 2A to 2I, where a triplet of 3 is used as the triplet data Y.
Here, it is supposed that the triplet data Y is a five-bit binary number "01010", which equals "10" in the decimal number system. In this case, the first and second constant generators 102 and 107 output the same decimal number "-3" to the first and second adding circuits 105 and 110 as the constants C1 and C2, respectively.
Initially, the binary content of each shift register 101, 106, and 111 is reset as "00000".
In the clock period T1 from the time t.sub.0 to the time t.sub.1, the value "0" in the MSB of the triplet data Y is inputted into the first shift register 101 through the serial input terminal 100. At this time, the content of the first shift register 101 is kept as "00000", because the inputted MSB value "0" of the triplet Y is set at the LSB in the content of the register 101. This binary content "00000" is outputted as the first register output R1.
The decimal number "-3" sent from the first constant generator 102 as the first constant C1 is subtracted from the first register output R1 of "00000" in the first adding circuit 105, thereby outputting the first subtraction result A1 of "11101" and the first borrow output B1 of "1".
Since the first borrow output B1 has a binary value "1" in this period T1, and inverted value "0" is inputted into the second shift register 106 through its input terminal 109 to be set at the LSB in the content of the register 106. Therefore, the content "00000" of the second shift register 106 is not changed.
Likewise, the binary content "00000" of the second shift register 106 is outputted as the second register output R2. The decimal number "-3" sent from the second constant generator 107 as the second constant C2 is subtracted from the second register output R2 of "00000" in the second adding circuit 110, thereby outputting the second subtraction result A2 of "11101" and the second borrow output B2 of "1".
Since the second borrow output B2 has a binary value "1" in this period T1, and inverted value "0" is inputted into the third shift register 111 through its input terminal 112 to be set at the LSB in the content of the register 111. Therefore, the content "00000" of the third shift register 111 is not changed.
Next, in the clock period T2 from the time t.sub.1 to the time t.sub.2, the value "1" in the second MSB of the triplet data Y is inputted into the first shift register 101 through the serial input terminal 100. At this time, the content of the first shift register 101 is changed to "00001", because the inputted value "1" of the triplet data Y is set at the LSB in the content of the register 101. This binary content "00001" is outputted as the first register output R1.
The decimal number "-3" sent from the first constant generator 102 as the first constant C1 is subtracted from the first register output R1 of "00001" in the first adding circuit 105, thereby outputting the first subtractions result A1 of "11110" and the first borrow output B1 of "1".
Since the first borrow output B1 has a binary value "1" in this period T2, an inverted value "0" is inputted into the second shift register 106 through its input terminal 109 to be set at the LSB in the content of the register 106. Therefore, the content "00000" of the second shift register 106 is not changed.
Similarly, the binary content "00000" of the second shift register 106 is outputted as the second register output R2. The decimal number "-3" sent from the second constant generator 107 as the second constant C2 is subtracted from the second register output R2 of "00000" in the second adding circuit 110, thereby outputting the second subtraction result A2 of "11101" and the second borrow output B2 of "1".
Since the second borrow output B2 has a binary value "1" in this period T2, an inverted value "0" is inputted into the third shift register 111 through its input terminal 112 to be set at the LSB in the content of the register 111. Therefore, the content "00000" of the third shift register 111 is not changed.
Next, in the clock period T3 from the time t.sub.2 to the time t.sub.3, the value "0" in the third MSB of the triplet data Y is inputted into the first shift register 101 through the serial input terminal 100. At this time, the content of the first shift register 101 is changed to "00010". This binary content "00010" is outputted as the first register output R1.
The decimal number "-3" is subtracted from the first register output R1 of "00010" in the first adding circuit 105. Thus, the first subtraction result A1 of "11111" and the first borrow output B1 of "1" are outputted.
In this period T3, an inverted value "0" of the binary value "1" of the first borrow output B1 is inputted into the second shift register 106 to be set at the LSB in the content of the register 106. Therefore, the content "00000" of the second shift register 106 is not changed.
Similarly, the decimal number "-3" is subtracted from the second register output R2 of "00000" in the second adding circuit 110. Thus, the second subtraction result A2 of "11101" and the second borrow output B2 of "1" are outputted.
An inverted value "0" of the binary value "1" of the second borrow output B2 is inputted into the third shift register 111 to be set at the LSB in the content of the register 111 in this period T3. Therefore, the content "00000" of the third shift register 111 is not changed.
In the clock period T4 from the time t.sub.3 to the time t.sub.4, the value "1" in the fourth MSB of the triplet data Y is inputted into the first shift register 101. At this time, the content of the first shift register 101 is changed to "00101". This binary content "00101" is outputted as the first register output R1.
The decimal number "-3" is subtracted from the first register output R1 of "00101" in the first adding circuit 105. Thus, the first subtraction result A1 of "00010" and the first borrow output B1 of "0" are outputted.
In this period T4, an inverted value "1" of the binary value "0" of the first borrow output B1 is inputted into the second shift register 106 to be set at the LSB in the content of the register 106. Therefore, the content "00000" of the second shift register 106 is not changed.
Similarly, the decimal number "-3" is subtracted from the second register output R2 of "00000" in the second adding circuit 110. Thus, the second subtraction result A2 of "11101" and the second borrow output B2 of "1" are outputted.
An inverted value "0" of the binary value "1" of the second borrow output B2 is inputted into the third shift register 111 to be set at the LSB in the content of the register 111 in this period T4. Therefore, the content "00000" of the third shift register 111 is not changed.
In the clock period T5 from the time t.sub.4 to the time t.sub.3, the content of the first shift register 101 is changed to "00100" and this binary content "00100" is outputted as the first register output R1. This is caused by the following reason.
Specifically, since the first borrow output B1 has a binary value "0" in the previous period T4, not only the value "0" in the LSB of the triplet data Y but also a binary value "00100" are simultaneously inputted into the first shift register 101. This binary value "00100" is obtained by shifting the value "00010" in the period T4 toward the MSB by one bit.
The decimal number "-3" is subtracted from the first register output R1 of "00100" in the first adding circuit 105. Thus, the first subtraction result A1 of "00001" and the first borrow output B1 of "1" are outputted.
In this period T5, an inverted value "0" of the binary value "1" of the first borrow output B1 is inputted into the second shift register 106 to be set at the LSB in the content of the register 106. Therefore, the content "11101" of the second shift register 106 is changed to "11110".
Similarly, the decimal number "-3" is subtracted from the second register output R2 of "11110" in the second adding circuit 110. Thus, the second subtraction result A2 of "11110" and the second borrow output B2 of "1" are outputted.
An inverted value "0" of the binary value "1" of the second borrow output B2 is inputted into the third shift register 111 to be set at the LSB in the content of the register 111 in this period T5. Therefore, the content "00000" of the third shift register 111 is not changed.
In the clock period T6 from the time t.sub.5 to the time t.sub.6, no effective data is inputted into the first shift register 101. This is because the triplet data Y of "3" has a five effective bits and this period T6 corresponds to a sixth bit from the start. Thus, the content of the first subtraction output Al in the previous period T5 with no shifting operation. As a result, the first subtraction output A1 is changed to "11110" and this binary content "11110" is outputted as the first register output R1.
The decimal number "-3" is subtracted from the first register output R1 of "11110" in the first adding circuit 105. Thus, the first subtract result A1 of "11110" and the first borrow output B1 of "0" are outputted in the clock period T6.
In this period T6, an inverted value "1" of the binary value "0" of the first borrow output B1 is inputted into the second shift register 106 to be set at the LSB in the content of the register 106. Therefore, the content "00001" of the second shift register 106 is changed to "00011".
Similarly, the decimal number "-3" is subtracted from the second register output R2 of "00011" in the second adding circuit 110. Thus, the second subtraction result A2 of "00000" and the second borrow output B2 of "0" are outputted.
An inverted value "0" of the binary value "1" of the second borrow output B2 is inputted into the third shift register 111 to be set at the LSB in the content of the register 111 in this period T6. Therefore, the content "00000" of the third shift register 111 is not changed.
In the clock period T7 from the time t.sub.6 to the time t.sub.7, the value "0" of the first borrow output B1 in the previous clock period T6 is inputted into the first shift register 101. Thus, the content "00001" of the first shift register 101 in the period T6 is changed to "00010". This binary content "00010" is outputted as the first register output R1.
The decimal number "-3" is subtracted from the first register output R1 of "00010" in the first adding circuit 105. Thus, the first subtraction result A1 of "11111" and the first borrow output B1 of "1" are outputted in the clock period T7.
In this period T7, because the first borrow output B1 has a binary value "0" in the previous period T6, the content "00000" of the second subtraction output A2 in the previous period T6 is inputted into the second shift register 106. Therefore, the content "00011" of the second shift register 106 is changed to "00000".
The decimal number "-3" is subtracted from the second register output R2 of "00011" in the second adding circuit 110. Thus, the second subtraction result A2 of "11111" and the second borrow output B2 of "1" are outputted.
An inverted value "1" of the binary value "0" of the second borrow output B2 in the previous period T6 is inputted into the third shift register 111 in this period T7. Therefore, the content "00000" of the third shift register 111 is changed to "00001".
With the above-described operation of the conventional triplet decoding circuit in FIG. 1, the lower two bits "01" in the content "00010" of the first shift register 101 in the period T6 give the original decimal value M3 of the triplet data Y. In other words, M3=1 in the decimal number system.
The lower two bits "01" in the content "00000" of the second shift register 106 in the period T7 give the original decimal value M2 of the triplet data Y. In other words, M2=0 in the decimal number system.
The lower two bits "01" in the content "00001" of the third shift register 11 in the period T7 give the original decimal value M1 of the triplet data Y. In other words, M1=1 in the decimal number system.
Consequently, the triplet data Y is decoded or expanded by substituting the given values M1, M2 and M3 into the above equation (1).
The same operation as above is applicable to the case of a triplet of 5, i.e., Y5, the timing chart of which is shown in FIGS. 3A to 3I.
The operation difference between the two triplet data Y3 and Y5 is that the first and second constants C1 and C2 outputted from the first and second constant generators 102 and 107 are set as "-5" by the selection signals S, and that eight clock periods of T1 to T8 are necessary for obtaining the original decimal values M1, M2, and M3. The other points are the same as those for the triplet of 3, and thus detailed description is omitted here.
In the case of the triplet data Y5, the lower three bits of the first selector output L1 represent the original decimal number M3 contained in the triplet data Y5, the lower three bits of the second selector output L2 represent the original decimal number M2 contained therein, and the lower three bits of the third register output R3 represent the original decimal number M1 contained therein.
As described above, with the conventional triplet decoding circuit in FIG. 1, the triplet data Y is serially inputted into the first shift register 101. Therefore, the decoding or expansion process takes a long time equal to or longer than the clock periods corresponding to the binary data length of the triplet data Y.
Specifically, seven clock periods are required for decoding a triplet of 3, while eight clock periods are required for decoding a triplet of 5.
Further, even when the triplet data Y has a decimal value over the predetermined allowable range (i.e., "1 to 26" for a triplet of 3, and "1 to 124" for a triplet of 5), the above conventional decoding circuit will perform the decoding or expansion processes, resulting in an erroneous output. To prevent this erroneous output, it is necessary to provide a circuit for examining the value of the triplet data Y prior to the decoding process.
However, this examining circuit causes another problem that the circuit scale and the decoding time are increased. For example, the processing time is increased to two times or more. This is because the value of the triplet data Y cannot be examined before all of the data Y are inputted into the conventional decoding circuit, in other words, because a specific time period is required for inputting all the triplet data Y before the decoding or expansion process.
Additionally, the conventional decoding circuit in FIG. 1 requires three shift registers and therefore, there is a disadvantage that the circuit scale is increased even when the above examining circuit is not provided.